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Sequencer

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What is a uvm sequencer?

A uvm_sequencer is a fundamental component of the testbench responsible for managing and coordinating the flow of transactions from the testbench to the design under test (DUT). It acts as an intermediary between the test sequences and the drivers, ensuring that transactions generated by test sequences are appropriately sent to the corresponding drivers for driving stimulus to the DUT.

Inbuilt Methods
Method Description
get_sequencer_id() Returns the sequencer's unique identifier within the testbench.
get_type() Returns the string representation of the sequencer's type name.
Code 
// Filename : basic_sequencer.sv

typedef basic_env;

class basic_sequencer extends uvm_sequencer#(basic_transaction);
    `uvm_component_utils(basic_sequencer)
    
    extern         function      new(string name, uvm_component parent);
    extern virtual function void build_phase(uvm_phase phase);
    extern virtual function void connect_phase(uvm_phase phase);
    extern virtual task          reset_phase(uvm_phase phase);
    extern virtual task          configure_phase(uvm_phase phase);
    extern virtual task          main_phase(uvm_phase phase);
    
endclass: basic_sequencer

//------------------------------------------------------------------//

function basic_sequencer::new(string name, uvm_component parent);
    super.new(name, parent);
    
endfunction: new

//------------------------------------------------------------------//

function void basic_sequencer::build_phase(uvm_phase phase);
    super.build_phase(phase);
    
endfunction: build_phase

//------------------------------------------------------------------//

function void basic_sequencer::connect_phase(uvm_phase phase);
    super.connect_phase(phase);
        
endfunction: connect_phase

//------------------------------------------------------------------//

task basic_sequencer::reset_phase(uvm_phase phase);
    super.reset_phase(phase);
    
endtask: reset_phase

//------------------------------------------------------------------//

task basic_sequencer::configure_phase(uvm_phase phase);
    super.configure_phase(phase);
    
endtask: configure_phase

//------------------------------------------------------------------//

task basic_sequencer::main_phase(uvm_phase phase);
    super.main_phase(phase);
    
endtask: main_phase
Theory Questions
    A UVM sequencer controls the flow of sequence items from sequences to the driver, managing arbitration and sequencing behavior.
    uvm_sequencer #(REQ) is the base class, where REQ is the sequence item type.
    Through the sequencer-driver handshake using TLM ports: `seq_item_port` in the driver and `seq_item_export` in the sequencer.
    Arbitration resolves which sequence gets control of the sequencer when multiple sequences are running concurrently.
    By calling `start(sequencer_handle)` from the test or another sequence.
    Yes, the sequencer can support multiple sequences using built-in arbitration mechanisms to manage them.
    The sequence will not run correctly, as it has no path to send sequence items to the driver.
    `uvm_sequencer` is a parameterized version built on `uvm_sequencer_param_base`, which provides the generic functionality for sequence control.
    In the agent's connect_phase, the driver’s `seq_item_port` is connected to the sequencer’s `seq_item_export`.
    Handling item requests, arbitrating between sequences, managing sequence lifecycles, and routing items to the driver.
    By enabling UVM verbosity messages and inserting print/debug statements in `body()`, `start()`, and `get_next_item()` phases of the sequence.
    If `is_active` is set to `UVM_ACTIVE`, the sequencer and driver are included in the agent; otherwise, they are excluded (for passive monitoring).
    No, typically one sequencer connects to one driver. For multiple drivers, multiple sequencers are instantiated.
    The sequencer arbitrates and issues items one at a time to the driver using `get_next_item()` and `item_done()`.
    `seq_item_export` (to the driver), and optionally `rsp_port` and `req_export` for handling responses and layered sequencers.