Hello and welcome to forkjoin.in! I'm Kesav, and this website is my way of giving back to the VLSI community. The platform serves as a practice question bank covering Verilog, SystemVerilog, UVM, and related verification methodologies. Whether you're a student, a professional, or preparing for interviews, I hope you find the content here helpful.
If you have questions, suggestions, or would like to contribute, please feel free to reach out at forkjoin.in@gmail.com . I'm always open to feedback and collaboration.
I'm grateful to the many people who help build and curate content for this platform. Special thanks to:
Indra
Vasu
Amit
Tazeer
Karan Chauhan
Tarun Burrah
Krishna Gopal Bajpai
Ram