Program Block

Overview

Program Block is used to create a modular and concurrent verification environment for testing the DUT, while modules are used to actually create the designs which will be synthesized and used in real world. The two blocks serve different purposes and are employed in different parts of the SystemVerilog testbench.

Unlike module, the code in program block runs in the "Re-Region" of the systemverilog event scheduling flow. This means that code from module will always be evaluated/executed first. This kind of order ensures segregation in code execution which ultimately enables an engineer to write better synchronized testbenches.

An example code snippet is given below to help understand this segregation.

module sv_module;
    
    initial
    begin
        $display( "Code inside Module Block runs first" );    
    end

endmodule

program sv_program;

    initial
    begin
        $display( "Code inside Program Block runs later" );    
    end

endprogram

// Output
//
// Code inside Module Block runs first
// Code inside Program Block runs later