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APB3 Testplan

Overview

This is the simple APB3 monitor check plan. The description is mentioned for every check along with the ERRRO ID and the spec section which describes the condition in detail. You can check the source code for the ERROR_ID definition and the VIP Monitor to better understand how these checks are being utilized.

Base Test Code

Base Sequence Code

Testplan ( 19 Tests ) ( Click on any test or sequence to go to the source code of it directly )

Testname

Sequence Name

Description

vip_amba_apb_master_sanity_test

vip_amba_apb_sanity_sequence

A basic sanity test where, a RD/WR transaction is geerated randomly

vip_amba_apb_master_random_test

vip_amba_apb_sanity_sequence

Random reads and writes happen in any order but within a working randomization space in order to hit any scoreboarding corner cases. Also this test is intended to fire multiple scenarios in any order with full randomization enabled. ( the last feature is not supported yet )

vip_amba_apb_master_read_test

vip_amba_apb_read_sequence

Simple APB read from master

vip_amba_apb_master_write_test

vip_amba_apb_write_sequence

Simple APB write from master

vip_amba_apb_master_write_read_test

vip_amba_apb_write_read_sequence

Multiple writes followed by reads

vip_amba_apb_master_read_to_read_test

vip_amba_apb_read_to_read_sequence

Back to back read test where in slave returns data immideatly. This is a optimistic scenarios since a slave takes time to return the data for the second read. To check if the back to back read follows the APB3 timing and handshake, this test is used.

vip_amba_apb_master_write_to_write_test

vip_amba_apb_write_to_write_sequence

Consecutive writes with minimum clock delay and random clock delay

vip_amba_apb_master_write_to_read_test

vip_amba_apb_write_to_read_sequence

Back to back read after write with minimum latency ( ie 1 clk )

vip_amba_apb_master_write_with_wait_test

vip_amba_apb_write_with_wait_sequence

Master write with delayed sampling from slave

vip_amba_apb_master_read_with_wait_test

vip_amba_apb_read_with_wait_sequence

Read with delayed data response from slave

vip_amba_apb_master_write_read_with_wait_test

vip_amba_apb_write_read_with_wait_sequence

Write followed by read with a delayed response

vip_amba_apb_master_read_err_inj_test

vip_amba_apb_read_err_inj_sequence

Read data with error injection ( Scoreboard will throw an error which helps us validate that the Scoreboard is working )

vip_amba_apb_master_write_pselx_timeout_test

vip_amba_apb_write_pselx_timeout_sequence

If RTL supports a PSELX timeout, then this test can be used

vip_amba_apb_master_read_pselx_timeout_test

vip_amba_apb_read_pselx_timeout_sequence

Read PSELX timeout test

vip_amba_apb_presetn_in_read_test

vip_amba_apb_presetn_in_read_sequence

In this test, the PRESETn is asserted once during a read transaction.

vip_amba_apb_presetn_in_write_test

vip_amba_apb_presetn_in_write_sequence

In this test, the PRESETn is asserted once during a write transaction. According to the specification, the Slave should not neccessarily update its data in case of a Write. Added to this, the Slave will reset like any other logic device.

vip_amba_apb_presetn_in_read_wait_test

vip_amba_apb_presetn_in_read_with_wait_sequence

In this test, the PRESETn is asserted once during a read with waits states transaction.

vip_amba_apb_presetn_in_write_wait_test

vip_amba_apb_presetn_in_write_with_wait_sequence

In this test, the PRESETn is asserted once during a write with wait states transaction after which a simple read is prerfomed to cross check the data in the slave's memory.

vip_amba_apb_master_pslverr_for_read_test

vip_amba_apb_pslverr_for_read_sequence

This test is used to check if the PRDATA bus has been driven with xs or 0s when an PSLVERR is asserted by the Slave. The X or 0 behaviour is specific to Slave and hence must use the provided configuration bit in the common parameters file.