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APB3 Monitor Checkplan

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Overview

This is the simple APB3 monitor check plan. The description is mentioned for every check along with the ERRRO ID and the spec section which describes the condition in detail. You can check the source code for the ERROR_ID definition and the VIP Monitor to better understand how these checks are being utilized.


ERROR_ID Definition Code

APB3 Monitor Code

Checkplan ( 13 Checks )

Error ID
Specification Version
Spec Section
Description

[ AMBA_APB_EID_000 ]
[ AMBA_APB3_v2 ]
[ - ]
Sample Error Message. No need to panic at all :P"

[ AMBA_APB_EID_001 ]
[ AMBA_APB3_v2 ]
[ 3.1.1 ]
PADDR Bus Value Changed during Access Phase"

[ AMBA_APB_EID_002 ]
[ AMBA_APB3_v2 ]
[ 3.1.1 ]
PWDATA Value Changed during Access Phase"

[ AMBA_APB_EID_003 ]
[ AMBA_APB3_v2 ]
[ 3.1.1 ]
PSTRB Bus Value Changed during Access Phase"

[ AMBA_APB_EID_004 ]
[ AMBA_APB3_v2 ]
[ 3.1.1 ]
PWRITE Bus Value Changed during Access Phase"

[ AMBA_APB_EID_005 ]
[ AMBA_APB3_v2 ]
[ - ]
PSELx Signal has not been de-asserted after the defined timeout"

[ AMBA_APB_EID_006 ]
[ AMBA_APB3_v2 ]
[ - ]
READ Data Mismatch has occured"

[ AMBA_APB_EID_007 ]
[ AMBA_APB3_v2 ]
[ - ]
READ is begin performend on an uninitialised or unwritten Memory Location"

[ AMBA_APB_EID_008 ]
[ AMBA_APB3_v2 ]
[ 3.4.0 ]
PSLVERR is high, which means the RDATA bus is supposed to be either all 0's or all x's"

[ AMBA_APB_EID_009 ]
[ AMBA_APB3_v2 ]
[ 3.2.0 ]
PSTRB must be LOW during a READ Transaction"

[ AMBA_APB_EID_010 ]
[ AMBA_APB3_v2 ]
[ 4.1.0 ]
PENABLE must be asserted only when PSELx is already asserted"

[ AMBA_APB_EID_011 ]
[ AMBA_APB3_v2 ]
[ 3.1.2 ]
PSELx must remain asserted for atleat 2 Clocks"

[ AMBA_APB_EID_012 ]
[ AMBA_APB3_v2 ]
[ 4.1.0 ]
PENABLE must be asserted immideatly after PSELx has been sampled as asserted for 1 Clock, ie Master should have moved into ACCESS Phase in 2 Clock Cycles"

[ AMBA_APB_EID_013 ]
[ AMBA_APB3_v2 ]
[ 3.3.0 ]
PREADY unexpectedly received. No ongoing transacton can be mapped to this runnaway signal assertion"