Testbench TOP is athe static module based block where the DUT is integrated with the quasi-static uvm environment where the uvm test is initiated. HAving a module based top is absolutly essential for integration and testing of any design. Given below is an example code of the testbench top.
Anbother key aspect to remember is that usually the file inclusions must be done here so that orderly compilation happens and there is no compilation issue.
Other purposes of top module:
Clock Generation// Filename : top_tb.sv // Include & Import UVM PKGs `include "uvm_macros.svh" import uvm_pkg::*; // Include The Testbench Files `include "basic_if.sv" `include "basic_transaction.sv" `include "basic_config.sv" `include "basic_coverage.sv" `include "basic_driver.sv" `include "basic_monitor.sv" `include "basic_sequencer.sv" `include "basic_sequence.sv" `include "basic_agent.sv" `include "basic_scoreboard.sv" `include "basic_env.sv" `include "base_test.sv" `include "sanity_test.sv" // -------------------- // Include the DUT here // -------------------- `include "design.sv" // -------------------- module top_tb; bit clk, rst_n; initial begin $display("Top"); end initial begin rst_n = 1'b0; #100ns; rst_n = 1'b1; end initial forever begin #5ns clk = ~clk; end basic_if inf (clk, rst_n); DUT DUT_instance ( .clk (inf.clk), .rst_n (inf.rst_n), .random_input (inf.random_input), .random_output (inf.random_output), .random_inout (inf.random_inout) ); initial begin uvm_config_db#(virtual basic_if)::set(null, "*", "basic_vif", inf); end initial begin run_test("sample_sanity_test"); end endmodule