A uvm_sequencer is a fundamental component of the testbench responsible for managing and coordinating the flow of transactions from the testbench to the design under test (DUT). It acts as an intermediary between the test sequences and the drivers, ensuring that transactions generated by test sequences are appropriately sent to the corresponding drivers for driving stimulus to the DUT.
| Method | Description |
|---|---|
| get_sequencer_id() | Returns the sequencer's unique identifier within the testbench. |
| get_type() | Returns the string representation of the sequencer's type name. |
// Filename : basic_sequencer.sv typedef basic_env; class basic_sequencer extends uvm_sequencer#(basic_transaction); `uvm_component_utils(basic_sequencer) extern function new(string name, uvm_component parent); extern virtual function void build_phase(uvm_phase phase); extern virtual function void connect_phase(uvm_phase phase); extern virtual task reset_phase(uvm_phase phase); extern virtual task configure_phase(uvm_phase phase); extern virtual task main_phase(uvm_phase phase); endclass: basic_sequencer //------------------------------------------------------------------// function basic_sequencer::new(string name, uvm_component parent); super.new(name, parent); endfunction: new //------------------------------------------------------------------// function void basic_sequencer::build_phase(uvm_phase phase); super.build_phase(phase); endfunction: build_phase //------------------------------------------------------------------// function void basic_sequencer::connect_phase(uvm_phase phase); super.connect_phase(phase); endfunction: connect_phase //------------------------------------------------------------------// task basic_sequencer::reset_phase(uvm_phase phase); super.reset_phase(phase); endtask: reset_phase //------------------------------------------------------------------// task basic_sequencer::configure_phase(uvm_phase phase); super.configure_phase(phase); endtask: configure_phase //------------------------------------------------------------------// task basic_sequencer::main_phase(uvm_phase phase); super.main_phase(phase); endtask: main_phase