forkjoin .in

Delays

Overview

Delays refer to the time intervals that you can specify to control the timing behavior of your digital design during simulation. Delays allow you to model the propagation of signals through gates, wires, and other elements in your design. Usually used to model real world circuit behaviour. They play a crucial role in accurately representing the timing characteristics of your design. The keywords for using delays are givn below:

#(delay_value)
#(delay_value)(timeunit)

a = #10 b; // ( inertial delay/ intra delay )
#10 a = b; // ( transport delay/ inter delay )

Theory Questions

Any delay mentioned after the assignment symbol is considered a intra delay. ( eg: a = #5 10; )

by Amritha Vishnu M

Normal delays are considered as inter delays. ( eg: #5 a = 10; )

by Amritha Vishnu M

module top;
    integer a,b;

    initial
    begin
        fork
            begin
                a = #5 100;
            end
            begin
                #5 b = 200;
            end
        join
        $display( "a : %0d, b : %0d", a, b );
        #5;
        $display( "a : %0d, b : %0d", a, b );
    end
endmodule

Locked Solution

module top;
    
    integer a,b,c;

    initial
    begin
        a = #4 100;
        b <= a;
        #1 c = #5 b;
        c <= 200;
    end

    initial
    begin
        $monitor( $time, "a : %0d, b : %0d, c : %0d", a, b, c );
    end

endmodule

Locked Solution

Coding Questions

module top;
    integer a,b;

    initial
    begin
        foreach
        begin
            #10 b = $urandom;
        end
    end

    assign a = @( posedge clk ) b;
endmodule

Locked Solution