Modules and port correspond to the fundamental code scope and the ability to connect two different blocks of codes in Verilog. Module is what you can call the "shell" of the verilog code. This module again has signals/pins which are called ports that are declared inside the module itself. These pins are a direct medium to connect different modules togather to create a larger functional block.
Keywords associated with modules & ports are listed below:-
module
endmodule
input
output
inout
A few other keywords associated with module concepts are listed below:-
generate
endgenerate
parameter
localparam
defparam