Home Projects Forum About Us

Datatypes

Prev : SystemVerilog History & Basics
Section Home Next : Arrays
Overview

Systemverilog datatypes are essentially the keywords which are used to store a certain kind of data. Most of the datatypes in Systemverilog are derived from the Verilog HDL language, with a couple of additional datatypes. The most important contribution of SystemVerilog in "Datatypes" is, the addition of "2 State Variable" datatypes. For more info regarding this topic, you can refer to the SystemVerilog Language Reference Maual ( LRM ).

Important Keywords

reg
wire
logic
bit
byte
integer
int
long/short
signed/unsigned
real
time

Theory Questions
    A 2-state datatype refers to data types that can only represent two values, which are 0 and 1; examples include bit and logic.
    Using 2-state datatypes in SystemVerilog, like bit, improves simulation performance and memory efficiency by not having to simulate the additional states (X for unknown and Z for high impedance) that 4-state types (reg and wire) manage.
    time is used to store values which correspond to the time numeric system, while in real floating point values are stored. They are one and the same in theory, but based on use, they have significantly different applications.
    It is used in floating point arithematic.
    Unsigned as time cannot be negative. 
    module top;
    logic out;
    reg [3:0] a,b;

    initial
    begin
        a = 5;
        b = 6; 
        out = b;
        $display( "out : %0d", out );
    end

    assign out = a;
endmodule

    module top;
    bit [31:0] A;
    reg [15:0] B;

    initial
    begin
        A = {32{1'b1}};
        B = A;
        $display( "B : %0b", B );
        B = ~B;
        $display( "B : %0b", B );
    end
endmodule 

    /*
B : 1111111111111111
B : 0
*/

    module top;

    time t;
    int i;

    initial
    begin
        i = 15;
        t = 15/2;
        $display( "Output : %0t", t );    
    end

endmodule

    /*
Output : 7.0
*/

    module top;
    bit a0;
    int a1;
    integer a2;
    real a3;
    time a4;
    wire a5;
    reg a6;
    logic a7;

    initial
    begin
       $display( "A0 : %0d", a0 ); 
       $display( "A1 : %0d", a1 ); 
       $display( "A2 : %0d", a2 ); 
       $display( "A3 : %0d", a3 ); 
       $display( "A4 : %0d", a4 ); 
       $display( "A5 : %0d", a5 ); 
       $display( "A6 : %0d", a6 ); 
       $display( "A7 : %0d", a7 ); 
    end
endmodule

    /*
A0 : 0 
A1 : 0
A2 : x 
A3 : x 
A4 : 0 
A5 : z 
A6 : x 
A7 : x  
*/
Coding Questions 
    module top;

    int M;

    initial begin
        M = $urandom;
        M[31] = 1; // Sinice int is signed :D
        $display( "M : %0d", M );
    end

endmodule