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Datatypes

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Overview

Verilog data types are common keywords used to declare variables. All verilog datatypes are 4-state ie, X , Z , 1 & 0 . They are further divided into two categories; reg and wire . The most commonly used keywords are given below.

integer
real
realtime
reg
time

wire
trireg
tri
triand
trior
tri1
tri0
uwure
wand
wor

Theory Questions ( Click to expand )
    The type of casting which is automatically invoked is called implicit casting . For example, when assigning a real to a reg variable.
    This is the kind of casting which is invoked manually . Just like in the previous example's case, to assign a real to reg, we do reg = '(real) 
    /*

1. reg (register): 
   - Default value: 1'bx (unknown) for each bit in the reg.

2. wire (net): 
   - Default value: z (high impedance or floating).

3. integer: 
   - Default value: 32'bx (unknown 32-bit value).

4. real (floating-point): 
   - Default value: 1.0 / 0.0 (NaN or Not a Number).

5. time (special integer type for simulation time): 
   - Default value: 64'bx (unknown 64-bit value).

*/
    A datatype which has the following posisble states : 0 , 1 , x and z
    To properly mimic a digital electrical system, the need for Z and X is necessary. 
    /*

1. reg (register): 
   - Default width: 1 bit (can be extended to multi-bit vectors).

2. wire (net): 
   - Default width: 1 bit (can be extended to multi-bit vectors).

3. integer: 
   - Default width: 32 bits.

4. real (floating-point): 
   - Default width: 64 bits (IEEE 754 double precision).

5. time (special integer type for simulation time): 
   - Default width: 64 bits.

*/
    real , integer and time
    In Verilog, a resolution table is used to determine the final value of a wire (or net) when multiple drivers are trying to assign different values to it. Since a wire can be driven by multiple sources, conflicts can arise when they try to assign different logic levels (e.g., 1 , 0 , z , or x ). Verilog resolves these conflicts by using a resolution table , which takes into account the driving strength of each source (such as strong , weak , or high impedance ) and the values being driven. For example, if one driver is applying a strong 1 and another is applying a weak 0 , the final value will be 1 because the stronger signal takes precedence. If two strong drivers apply conflicting values ( strong 1 and strong 0 ), the result will be x (unknown), indicating a logic conflict. This mechanism ensures predictable behavior when wires are driven by multiple sources.
    In Verilog, reg and wire are two fundamental data types with distinct usage and behavior. A reg is used to store values in procedural blocks like always , initial , or task and behaves like a memory element, holding its value until explicitly changed. In contrast, a wire represents physical connections and is driven by continuous assignments like assign or the output of modules or gates, updating immediately when the driving signal changes. A reg can be assigned inside procedural blocks, while a wire cannot; it must be driven by continuous assignments. The default value of a reg is 1'bx (unknown), whereas a wire defaults to z (high impedance). Essentially, reg is used for storing values, while wire models combinational logic or connections.
Coding Questions ( Click to expand ) 
    module top;

    //reg (register): 
    reg A;
    //wire (net): 
    wire B;
    //integer: 
    integer C;
    //real (floating-point): 
    real D;
    //time (special integer type for simulation time):
    time E;

    initial
    begin
        $display("Reg : %0d",A);
        $display("Wire : %0d",B);
        $display("Integer : %0d",C);
        $display("Real : %0d",D);
        $display("Time : %0d",E);
    end

endmodule

    module top;
    
    //reg (register): 
    reg A;
    //wire (net): 
    wire B;
    //integer: 
    integer C;
    //real (floating-point): 
    real D;
    //time (special integer type for simulation time):
    time E;

    initial
    begin
        $display("Reg : %0d",$bits(A));
        $display("Wire : %0d",$bits(B));
        $display("Integer : %0d",$bits(C));
        $display("Real : %0d",$bits(D));
        $display("Time : %0d",$bits(E));
    end

endmodule

    module top;

    integer A;

    initial
    begin
        A = $urandom;
        A[31] = 0;

        $display("A : %0d", A);
        A[31] = 1;
        $display("A : %0d", A);


    end

endmodule