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Verilog History & Basics

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Overview

SystemVerilog was introduced in 2002 as the IEEE 1800 standard. It currently has its latest revision, which came out in 2018. SystemVerilog is a language which is primarily a superset of Verilog, with the added features of high level programming which make this language convinent to code the models and tesetbenches. Alternately, this language is still used to code RTL designs just like its predecessor, Verilog.

Theory Questions
    The conventional HLL Procedural languages were not suitable for modelling the behaviour of digital electronic ciscuits which eventually led to creation of a HDL all togather, that we know today as VHDL . Later, Verilog and SysytemVerilog were introduced.
    Verilog is a HDL which means its a "Hardware Description Language". This implies that this is exclusively written to mimic a digital hardware system, unlike a traditional computer program.
    Some types of simulators avialable are : Cycle Driven and Event Driven .
    QuestaSim, Xcelium, Synopsys VCS and Verilator.
    Dataflow , Structural , Behavioural , Gate Level and Switch Level .
    No, its not possible to a usable extent.
    VHDL, BlueSpec and pyHDL. (there are more which can be explored)
    Its not possible to easily scale the TB to a different larger TB. Also, the biggest concern is with the race around problem between TB and DUT.
    No. It only mimics the final behaviour which gives us the illusion of parallelism. At its core, its still a sequentially executed progrm by the CPU.
    Verilog has a concept called "time step". Within this timestep, when a DUT is driving a signal and in that moment if the TB samples the data early, then the TB fails to capture the actual driven value. This mis-sampling or mis-driving is called "Race Around" .
    Yes, but mostly by designers. For verification, the engineers strictly follow SystemVerilog.