SystemVerilog was introduced in 2002 as the IEEE 1800 standard. It currently has its latest revision, which came out in 2018. SystemVerilog is a language which is primarily a superset of Verilog, with the added features of high level programming which make this language convinent to code the models and tesetbenches. Alternately, this language is still used to code RTL designs just like its predecessor, Verilog.