A uvm_sequence is a fundamental component used to define and control a sequence of transactions or operations that verify specific functionalities or scenarios in the design under test (DUT). It serves as a container for generating stimulus and can be reused across different parts of the testbench to efficiently verify various aspects of the DUT's behavior.
| Functionality | Description |
|---|---|
| Transaction Generation | The primary purpose of a uvm_sequence is to generate sequences of transactions or events that represent specific test scenarios. Each transaction typically models a stimulus that is applied to the input ports of the DUT. |
| Base Class Extension | The uvm_sequence is a user-defined class that extends the uvm_sequence base class provided by UVM. The user can customize the sequence by defining the necessary behavior and transactions specific to the test scenario. |
| Sequence Library | Sequences can be organized into a sequence library, allowing them to be reused and shared across different testbenches or test cases, promoting modularity and reusability in the verification environment. |
| Randomization | The uvm_sequence supports randomization, allowing the test scenarios to be randomized and varied during the verification process. Randomization helps explore different input scenarios and uncover corner cases in the DUT. |
| Sequencer Interaction | The uvm_sequence interacts with a sequencer, which acts as a traffic cop for managing the order and flow of transactions to the DUT. The sequence instructs the sequencer to start generating the specified transactions. |
| Constraint-Based Generation | Sequences can include constraints to control the properties of the generated transactions. Constraints help ensure that the generated stimulus adheres to specified conditions, improving the efficiency and effectiveness of the verification. |
| Data Collection | The sequence may collect data during the execution, which can be used for coverage analysis, logging, or comparison with expected results. |
| Wait and Sync Points | A sequence may include wait and sync points to synchronize with the DUT's responses or wait for specific conditions before proceeding with the next transaction. |
| Response Handling | The uvm_sequence can process the DUT's responses captured by a monitor or checker, making it possible to verify the correctness of the DUT's behavior. |
| Sequencer Arbitration (Optional) | If multiple sequences are running concurrently, the sequence might need to handle sequencer arbitration to ensure fair access to the sequencer by different sequences. |
// Filename : basic_sequence.sv class basic_sequence extends uvm_sequence; `uvm_object_utils(basic_sequence) `uvm_declare_p_sequencer(basic_sequencer) basic_config cfg; extern function new(string name = "basic_sequence"); extern virtual task pre_body(); extern virtual task body(); extern virtual task post_body(); endclass: basic_sequence //------------------------------------------------------------------// function basic_sequence::new(string name); super.new(name); endfunction: new //------------------------------------------------------------------// task basic_sequence::pre_body(); super.pre_body(); endtask: pre_body //------------------------------------------------------------------// task basic_sequence::body(); // Create Sequence Item // Randomize Item // Send Item endtask: body //------------------------------------------------------------------// task basic_sequence::post_body(); super.post_body(); endtask: post_body