What is a uvm monitor?

A "uvm_monitor" is an essential element of a testbench that is responsible for observing the activity on the DUT. Its main purpose is to capture the output signals and other relevant data from the DUT's interface and convert them into transaction-level information that can be analyzed and checked for correctness during the verification process.

Code
// Filename : basic_monitor.sv

class basic_monitor extends uvm_monitor;
  `uvm_component_utils(basic_monitor)

	extern         function      new(string name, uvm_component parent);
	extern virtual function void build_phase(uvm_phase phase);
	extern virtual function void connect_phase(uvm_phase phase);
	extern virtual function void end_of_elaboration_phase(uvm_phase phase);
	extern virtual function void start_of_simulation_phase(uvm_phase phase);
	
	extern virtual task  main_phase(uvm_phase phase);
	
	extern virtual function void extract_phase(uvm_phase phase);
	extern virtual function void check_phase(uvm_phase phase);
	extern virtual function void report_phase(uvm_phase phase);
	extern virtual function void final_phase(uvm_phase phase);
	
endclass

//------------------------------------------------------------------//

function basic_monitor::new(string name, uvm_component parent);
	super.new(name, parent);

endfunction: new

//------------------------------------------------------------------//

function void basic_monitor::build_phase(uvm_phase phase);
	super.build_phase(phase);
	
endfunction: build_phase

//------------------------------------------------------------------//

function void basic_monitor::connect_phase(uvm_phase phase);
	super.connect_phase(phase);
	
endfunction: connect_phase

//------------------------------------------------------------------//

function void basic_monitor::end_of_elaboration_phase(uvm_phase phase);
	super.end_of_elaboration_phase(phase);
	
endfunction: end_of_elaboration_phase

//------------------------------------------------------------------//

function void basic_monitor::start_of_simulation_phase(uvm_phase phase);
	super.start_of_simulation_phase(phase);
	
endfunction: start_of_simulation_phase

//------------------------------------------------------------------//

task basic_monitor::main_phase(uvm_phase phase);
	super.main_phase(phase);
	phase.raise_objection(this);
	
	phase.drop_objection(this);
endtask: main_phase

//------------------------------------------------------------------//

function void basic_monitor::extract_phase(uvm_phase phase);
	super.extract_phase(phase);
	
endfunction: extract_phase

//------------------------------------------------------------------//

function void basic_monitor::check_phase(uvm_phase phase);
	super.check_phase(phase);
	
endfunction: check_phase

//------------------------------------------------------------------//

function void basic_monitor::report_phase(uvm_phase phase);
	super.report_phase(phase);
	
endfunction: report_phase

//------------------------------------------------------------------//

function void basic_monitor::final_phase(uvm_phase phase);
	super.final_phase(phase);
	
endfunction: final_phase
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