Overview

In Verilog, randomization refers to the process of generating random or pseudo-random values for variables or signals during simulation. Randomization is used to create various test scenarios, stimulate different input conditions, and uncover corner cases in a design's behavior. It's a crucial technique in functional verification to ensure that a design functions correctly across a wide range of possible inputs.

$random
$urandom
$random_range( min, max )

Theory Questions
Coding Questions
    module top;
    
        reg [31:0] RAND;
    
        initial
        begin
            RAND = $urandom;
            RAND[0] = 1;
            
            $display("RAND : %0d", RAND);
        end
    
    endmodule
    
    function getNum;
        return $urandom%100;    
    endfunction
    
    module top;
    
        reg [31:0] RAND;
    
        initial
        begin
            RAND = getNum();
            
            $display("RAND : %0d", RAND);
        end
    
    endmodule
    
    function getMaxMinRange( integer max, integer min );
        return ($urandom%(max-min))+min+1;    
    endfunction
    
    module top;
    
        reg [31:0] RAND;
    
        initial
        begin
            RAND = getMaxMinRange(30,5);
            
            $display("RAND : %0d", RAND);
        end
    
    endmodule
    
    function getRand;
        return ($urandom/3)*3;
    endfunction
    
    module top;
    
        reg [31:0] RAND;
    
        initial
        begin
            RAND = getRand();
            
            $display("RAND : %0d", RAND);
        end
    
    endmodule
    
    Locked Solution
    Locked Solution
    function integer getWeight();
        return {$urandom,(($urandom%100)<20)?1'b0:1'b1};
    endfunction
    
    module top;
    
        integer RAND;
        integer i;
    
        initial
        begin
            for( i = 0; i < 20; i=i+1 )
            begin
                RAND = getWeight();
                $display("RAND : %0d", RAND);
            end
        end
    
    endmodule
    
    function reg [31:0] getUs();
        return {$urandom>>1};
    endfunction
    
    module top;
    
        integer RAND;
    
        initial
        begin
            RAND = getUs();
            $display("RAND : %0d", RAND);
        end
    
    endmodule
    
    Locked Solution
    function reg [63:0] get64();
        return {$urandom,$urandom};
    endfunction
    
    module top;
    
        reg [63:0] RAND;
    
        initial
        begin
            RAND = getUs();
            $display("RAND : %0d", RAND);
        end
    
    endmodule