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Operators

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Overview

Just like any other language, verilog also uses operators. Most of these you would be familiar from other high level languages. But, there are a few operators which are more consistent with only an HDL laguage. Following is the list of all operators which would be required by an engineer to remember.


Operator Description
{ }, { { } } Concatenation, replication
+, -, *, /, ** Arithematic
% Modulus
>, >=, <=, < Relational
! Logical Negation
&& Logical AND
|| Logical OR
== Logical Equality
!= Logical Inequality
=== Case Equality
!== Case Inequality
~ Bitwise INVERT
& Bitwise AND
| Bitwise OR
^ Bitwise XOR
^~, ~^ Bitwise Equivalence
&, ~&, |, ~|, ^, ~^, ^~ Reduction Operators
<< Logical Left Shift
>> Logical Right Shift
<<< Arithematic Left Shift
>>> Arithematic Right Shift
? : Conditional Operator / Ternary Operator

Theory Questions
    +: and -: are used for slicing.
    Even in verilog, the operator precedence needs to be followed in order to make solving expressions seamless. For example, in a+b/2%4-10 , its very difficult to tell what is the output due to the lack of brackets. This is solved if the operator precedence is followed.
    && is logical AND, while & is bit-wise AND.
    == compares only 2-state values while === compares 4-state values.
    Reduction operators are basically any bit-wise operators placed in the LSH front of any variable. It essentially does that bit-wise operation on all the bits of the vector among themselves, ie in case of reg [3:0] M, if we call ^M , this is nothing but M[3]^M[2]^M[1]^M[0]
    ! is logical, while ~ is bit-wise.
Coding Questions 
    module top;

    reg [31:0] VAR = $random;

    initial
    begin
        reg PARITY;

        PARITY = ^VAR;

        $display("Parity Is : %0d", PARITY);            
    end

endmodule

    module top;

    integer ADDR = 103;

    initial
    begin
        $display("Address Offset From Nearest Segment Boundary : %0d", ADDR-((ADDR/(128/4))*(128/4)));           
    end

endmodule

    module top;

    integer ADDR_1 = 678;
    integer ADDR_2 = 811;
    integer SEG_SIZE = 1024/8;

    initial
    begin
        $display("Address 1 Offset From Nearest Segment Boundary : %0d", ADDR_1-((ADDR_1/(SEG_SIZE))*SEG_SIZE));           
        $display("Address 2 Offset From Nearest Segment Boundary : %0d", ADDR_2-((ADDR_2/(SEG_SIZE))*SEG_SIZE));           
    end
endmodule

    module top;

    reg [31:0] NUM;

    initial
    begin
        reg [3:0] HEX_VAL = $urandom; // Hex symbol is picked

        // Now populate the whole of NUM with this hex symbol
        integer i = 0;
        for( i = 0; i < 32/4; i = i + 1 )
        begin
            NUM[i*4+:4] = HEX_VAL;
        end

        $display("Output : %h",NUM);
    end

endmodule