System tasks are the inbuilt SYstemVerilog methods which serve very specific functionality. They in most cases can be used anywhere in the SystemVerilog language, including the assertions , constraints and coverage . Some of the most commonly used system tasks are listed below:
Time system tasks:
$time
$realtime
Simulation control system tasks:
$finish
$stop
Data query system tasks:
$bits
$typename
Math system tasks:
$clog2
$log10
$ceil
$floor
Bit vector system tasks:
$countbits
$onehot
$isunknown
$countsones
More can be found in the SystemVerilog 1800 LRM Section 20.1